At Six Five Summit 2026, Marvell executives said inference models drove KV cache to expand roughly 10x in nine months, pushing copper interconnect to performance limits and making optical interconnect and memory expansion core variables for compute scaling. Marvell is advancing NPO and CPO paths, analog SerDes can cut power by ~4x, and it introduced a photonic fabric memory device with a 32TB external memory pool; CXL products have seen considerable demand.
At the Six Five Summit 2026, Sumit Sadana, senior adviser to Micron's CEO, said memory has become the core bottleneck determining AI performance, with meaningful new capacity not arriving until after 2028. He disclosed Micron's capex plans: over $13 billion in fiscal 2025, doubled in fiscal 2026, and more than $45 billion expected in fiscal 2027, plus a $250 billion U.S. investment. He also said humanoid robots will become the largest incremental memory market, requiring hundreds of GB of DRAM and several TB of NAND per device.